Many of today's battery powered consumer products require more than one power supply voltage levels to operate. For example, a Central Processing Unit (CPU) for a laptop may be designed to operate at 2.9 volts while the hard disk drive operates at 5 volts. Instead of providing several sources of power supply, these products typically use a single power supply source and generate other supply levels with DC to DC converters. The DC to DC conversion is typically performed by the power supply regulator circuitry that is universally provided in battery operated electronic products.
There are basically two types of power supply regulators, linear and switching regulators. Linear regulators rely on a linear control element with a feedback to regulate a constant voltage. When a linear regulator is used as a DC to DC converter, there is an appreciable amount of power dissipation.
In a switching regulator, a transistor operating as a switch (switch transistor) periodically applies the input voltage across an inductor for short intervals. Since the input voltage is switched ON and OFF to transfer just enough charge to the load, an ideal switching regulator dissipates zero power. There are several types of switching regulators, for example, step-down, step-up, and inverting regulators. Although there are different ways to realize switching conversion, a common method uses inductor and capacitor as energy storage elements and a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) as the switch transistor.
MOSFETs have limit on voltage stress across terminals for reliable operation. For a switching regulator implemented in a given technology, if the input voltage supplied to the switch transistors (MOSFETs) of a switching stage is higher than the limit on voltage stress, MOSFETs of the switching stage may face reliability issues. A known method to rectify these reliability issues in switching stages is to cascode a set of MOSFETs. In a cascoded structure of MOSFETs, when an input voltage which is higher than the limit on voltage stress is supplied to a set of MOSFETs, the input voltage will be shared among the set of MOSFETs. One problem which arises in such a cascode structure is to ensure that the input voltage is equally shared among the MOSFETs. Another problem is to divide the stress equally even in the presence of glitches at the nodes caused by switching transients.
FIG. 1 illustrates a simplified circuit diagram of a capacitor held cascode structure 100 of a switching regulator according to the prior art. The capacitor held cascode structure 100 includes a series connected structure of a P-type switch transistor (PMOS) 115, a P-type cascode transistor (PMOS) 120, an N-type cascode transistor (NMOS) 125 and an N-type switch transistor (NMOS) 130. A bias voltage (PCAS BIAS) 135 is supplied to the P-type cascode transistor 120 and another bias voltage (NCAS BIAS) 140 is supplied to the N-type cascode transistor 125. A capacitor 105 is connected in parallel with the series combination of the P-type switch transistor 115 and P-type cascode transistor 120. Similarly, a capacitor 110 is connected in parallel with the series combination of the N-type switch transistor 125 and N-type cascode transistor 130. The values of capacitors 105 and 110 are selected to be larger than any parasitic capacitance of the switching transistors, as explained in more detail in the next paragraph.
Further explaining the need of capacitors with large capacitance value, a parasitic capacitance exists between all the terminals of the MOSFETs (drain to gate, source to gate and drain to source). Because of this parasitic capacitance between drain and gate, a rapid change in output potential during a switching transition can result in a corresponding rapid change in the potential on a node 118 between the P-type switching transistor 115 and P-type cascode transistor 120. This rapid potential change can exceed the maximum safe potential difference across the terminals of the transistor and can therefore result in premature failure of the transistor. A known method for rectifying these reliability issues is to specify values for capacitor 105 that are significantly higher than the values of the parasitic capacitance of the switching transistors. In on-chip switch implementations, capacitors of such large capacitance value occupy a large die area. Further, while increasing the values of the capacitor 105 holds the gate of the P-type cascode transistor 120 at a constant value with respect to the input voltage, it does not maintain all the transistors in reliable region of operation when the output transitions from low voltage to high voltage when there will be glitches in the input voltage node 145, the output node 155 and ground voltage node 150 due to L*di/dt, wherein L is the bond wire inductance and di/dt is the rate of change of current. In such case, stress occurs at the P-type cascode transistor 120. Similar reliability issues can occur on N-type switch transistor 125 and N-type cascode transistor 130.
In light of the foregoing discussion, there is a need to provide a reliable and area efficient switch cascode structure in cascode implementations.